1. Field of the Invention
The present invention relates to a p-type MOS (Metal Oxide Semiconductor) transistor of LDD (Lightly Doped Drain-Source) structure and a manufacturing method thereof.
2. Description of the Related Art
Typical MOS transistors currently used in logic circuits and the like have an LDD structure as shown in FIG. 1. Specifically, p-type MOS transistor 100 of LDD structure illustrated in FIG. 1 is configured such that gate insulating film 102 in a predetermined pattern is disposed on the surface of n-type silicon substrate 101, p-type gate electrode 103 is disposed thereon, and sidewalls 104 are formed on both sides of gate insulating film 102 and gate electrode 103. Deeply doped p-type source/drain areas 105 are formed in the surface portions of silicon substrate 101 on the outer sides of the portions on which sidewalls 104 are formed. Lightly doped p-type source/drain areas 106 are formed in the surface portions of silicon substrate 101 on the inner sides of the deeply doped p-type source/drain areas 105. Channel area 107 is interposed between paired lightly doped p-type source/drain areas 106.
In the configuration, the interface between gate insulating film 102 and each sidewall 104 is close to the interface between channel area 107 and each source/drain area 106. That is, MOS transistor 100 is configured such that the plane corresponding to the interface between gate insulating film 102 and each sidewall 104 substantially coincides with or opposite in close proximity to the plane corresponding to the interface between channel area 107 and each source/drain area 106.
Since MOS transistor 100 configured as mentioned above has an LDD structure in which lightly doped source/drain areas 106 are located on the inner sides of deeply doped source/drain areas 105, it can restrict the occurrence of hot carriers and prevent a reduction in breakdown voltage.
In the aforementioned MOS transistor 100, gate insulating film 102 is formed of a silicon thermal oxidation film formed on the surface of silicon substrate 101, and source/drain areas 105, 106 and gate electrode 103 include a p-type impurity such as boron ion-implanted therein for allowing them to serve as p-channels.
A method of manufacturing MOS transistor 100 as described above is simply described in the following.
The surface of silicon substrate 101 is first subjected to thermal treatment to form a silicon thermal oxidation film on the entire surface. Gate electrode 103 in a predetermined pattern is formed on the surface of the silicon thermal oxidation film. Dry etching is performed on the silicon thermal oxidation film with gate electrode 103 used as a mask. The etching removes the portion of the silicon thermal oxidation film on the surface of silicon substrate 101 which is not masked by gate electrode 103. The silicon thermal oxidation film remaining under gate electrode 103 is to serve as gate insulating film 102.
Next, a p-type impurity is ion-implanted into gate electrode 103 to make gate electrode 103 p-type. A p-type impurity is ion-implanted into the silicon substrate at the positions where lightly doped source/drain areas 106 are to be formed and then annealing is performed for activation, thereby forming lightly doped source/drain areas 106. Sidewalls 104 are formed on both sides of gate insulating film 102 and gate electrode 103 on the surface of the portions in silicon substrate 101 where source/drain areas 106 are formed. Finally, a p-type impurity is ion-implanted in the surface portions of silicon substrate 101 with sidewalls 104 used as masks and annealing is performed for activation to form deeply doped source/drain areas 105. In this manner, p-type MOS transistor 100 of LDD structure is completed.
In the aforementioned transistor manufacturing method, lightly doped source/drain areas 106 are formed by implanting the p-type impurity into the surface portions of silicon substrate 101 with gate electrode 103 used as a mask and performing annealing, and deeply doped source/drain areas 105 are formed by implanting the p-type impurity into the surface portions of silicon substrate 101 with sidewalls 104 used as masks and performing annealing. Thus, it is possible to simply and reliably form the LDD structure including lightly doped source/drain areas 106 and deeply doped source/drain areas 105.
In the aforementioned p-type MOS transistor 100, however, when the impurity is implanted into silicon substrate 101 and then the annealing is performed to form source/drain areas 105, 106, the p-type impurity implanted into gate electrode 103 may be diffused even to channel area 107 in silicon substrate 101 through gate insulating film 102. In this case, since channel area 107 in silicon substrate 101 which should be of n-type becomes p-type, the performance of p-type MOS transistor 100 is degraded.
To solve the problem, Japanese Patent Laid-open Publication No. 313114/98, for example, discloses a MOS transistor in which a gate insulating film is formed of a silicon oxynitride film to prevent a p-type impurity from being diffused to a channel area from a gate electrode.
The present inventors, however, have found, from actual manufacturing of a p-type MOS transistor having a gate insulating film formed of a silicon oxynitride film, that while it can prevent the diffusion of a p-type impurity from a gate electrode to a channel area, BT (Bias Temperature) characteristics show more degradation than that of one having a gate insulating film formed of a silicon thermal oxidation film. Studies to find a cause have revealed that the silicon oxynitride film contains positive fixed charge therein from the time of film formation, and the amount of the accumulated positive fixed charge is significantly increased due to BT stress to readily increase of the interface state density. Thus, a p-type MOS transistor having a gate insulating film formed of a silicon oxynitride film is susceptible to degradation of BT characteristics such as a shift of threshold voltage or degradation of on-state current.
In addition, detailed analysis of the BT characteristics have shown that a shift of threshold voltage or degradation of on-state current tends to occur due to fixed charge on both end portions of the gate insulating film close to source/drain areas, and the BT characteristics are affected to a lesser extent in the central portion of the gate insulating film away from the source/drain areas.
Accordingly, it is possible to prevent diffusion of a p-type impurity from a gate electrode to a channel area in a p-type MOS transistor and degradation of BT characteristics by forming the central portion of a gate insulating film of a silicon oxynitride film and forming each of both end portions of a silicon thermal oxidation film. A p-type MOS transistor of such structure is disclosed, for example, in Japanese Patent Laid-open Publication No. 102482/93. The p-type MOS transistor disclosed in the Laid-open publication has a structure including overlapping gate electrode and source/drain areas, in which the central portion of the gate insulating film is formed of a silicon oxynitride film while both end portions of the gate insulating film are each formed of a silicon thermal oxidation film. More specifically, as shown in FIG. 2, p-type MOS transistor 120 disclosed in the aforementioned Laid-open publication has gate insulating film 122 and p-type gate electrode 123 disposed in turn on the surface of n-type silicon substrate 121. Gate insulating film 122 is formed of silicon oxynitride film 128 only in the central portion, and formed of silicon thermal oxidation film 129 in each of both end portions. P-type deeply doped source/drain areas 125 and p-type lightly doped source/drain areas 126 are formed in the surface portions of silicon substrate 121. Deeply doped source/drain areas 125 are primarily formed at the positions on the outer sides of gate electrode 123, while lightly doped source/drain areas 126 are formed at the positions on the outer sides of silicon oxynitride film 128 which is the central portion of gate insulating film 122. Channel area 127 is formed only under silicon oxynitride film 128 which is the central portion of gate insulating film 122. Sidewalls are formed on neither side of gate insulating film 122 and gate electrode 123, and interlayer insulating film 124 in the shape of an inverted U is formed to cover the top surface and sides surfaces of gate electrode 123.
Since p-type MOS transistor 120 of the aforementioned structure has overlapping lightly doped source/drain areas 126 and gate electrode 123, the occurrence of hot carriers can be restrained in the LDD structure. In addition, since both end portions of gate insulating film 122 located over lightly doped source/drain areas 126 are each formed of silicon thermal oxidation film 129, degradation of BT characteristics can be prevented. Furthermore, since the central portion of gate insulating film 122 located over channel area 127 is formed of silicon oxynitride film 128, it is possible to prevent diffusion of the p-type impurity from gate electrode 123 to silicon substrate 121.
Simple description is hereinafter made for a method of manufacturing the aforementioned MOS transistor 120. Silicon thermal oxidation film 129 is first formed on the surface of silicon substrate 121. A polysilicon mask (not shown) in a predetermined pattern is disposed on silicon thermal oxidation film 129 and nitriding is performed thereon. Only the portion of silicon thermal oxidation film 129 not covered with the polysilicon mask is nitrided to form silicon oxynitride film 128. Silicon thermal oxidation film 129 covered with the polysilicon mask is not nitrided but remains as it is.
Next, the polysilicon mask is removed to form gate electrode 123. A p-type impurity is ion-implanted into silicon substrate 121 at the positions where deeply doped source/drain areas 125 are to be formed with gate electrode 123 used as a mask. Interlayer insulating film 124 is formed in the shape of an inverted U to cover the top surface and side surfaces of gate electrode 123. Then, the entirety is heated to high temperature for annealing. The p-type impurity included in gate electrode 123 is diffused to the positions where lightly doped source/drain areas 126 are to be formed through silicon thermal oxidation film 129 and the impurities diffused to silicon substrate 121 are activated to complete deeply doped and lightly doped source/drain areas 125, 126.
In the transistor manufacturing method, however, process control is extremely difficult as compared with typical ion implantation since the p-type impurity in gate electrode 123 is diffused to silicon substrate 121 to form lightly doped source/drain areas 126.
It is difficult to independently control diffusion of an impurity in a vertical direction (depth direction) and a horizontal direction (width direction). In other words, diffusion in the vertical direction and diffusion in the horizontal direction proceed in substantially the same degrees. Thus, when the diffusion of the impurity is used to form lightly doped source/drain areas 126 as described above, each of the areas has a width in the horizontal direction substantially equal to a depth in the vertical direction, and thus it is impossible to freely form lightly doped source/drain areas in arbitrary shapes, thereby possibly causing the inability to form lightly doped source/drain areas in desired ideal shapes.
In addition, since the p-type impurity in gate electrode 123 is diffused to silicon substrate 121 as described above, it is difficult to control such that the p-type impurity in gate electrode 123 has a proper concentration after the diffusion. Thus, excessive or insufficient impurity concentrations readily occur in lightly doped source/drain areas 126 and gate electrode 123 to make it difficult to obtain optimal impurity concentrations in both of them.
In the aforementioned method, the polysilicon mask is used for partially nitriding silicon thermal oxidation film 129 to form silicon oxynitride film 128. In the method, however, damage due to etching is caused in the central portion of gate insulating film 122 when patterning is performed with the polysilicon mask, and damage is caused on the entire surface of gate insulating film 122 when the polysilicon mask is removed.
Most of the aforementioned problems become serious as the scale of integration is increased in MOS transistor 120. Therefore, it is not a practical idea to manufacture MOS transistor 120 using the circuit manufacturing method described in the aforementioned Laid-open publications at current factories where high-integration circuit products are mass-manufactured.
In view of the aforementioned problems, it is an object of the present invention to provide a p-type MOS transistor capable of preventing diffusion of a p-type impurity in a gate electrode to a silicon substrate and preventing degradation of BT characteristics, and a manufacturing method thereof.
A MOS transistor of the present invention comprises a gate insulating film disposed on the surface of a silicon substrate, a p-type gate electrode formed on the gate insulating film, and sidewalls formed on both sides of the gate insulating film and the gate electrode. A pair of p-type source/drain areas is provided in surface portions of the silicon substrate, and a channel area is located between the source/drain areas. The gate insulating film comprises a central portion formed of a nitride insulating film containing at least nitrogen and both end portions located on both sides of the central portion and each formed of an oxide insulating film containing oxygen and no nitrogen.
With the configuration, the nitride insulating film of the gate insulating film can prevent the p-type impurity doped into the gate electrode from being diffused to the silicon substrate during thermal treatment. Since the portions of the gate insulating film in contact with the source/drain areas are each formed of the oxide insulating film, degradation of BT characteristics can be prevented. In addition, the source/drain areas can be formed in desired shapes and at desired concentrations of doping to achieve favorable characteristics of the transistor.
The LDD structure may be adopted, whose source/drain areas comprise lightly doped source/drain areas located on inner sides in contact with the channel area and deeply doped source/drain areas located on the outer sides of the lightly doped source/drain areas. In this case, the deeply doped source/drain areas and lightly doped source/drain areas can be simply formed by using the sidewalls.
The oxide insulating film thicker than the nitride insulating film allows favorable functions as the LDD structure and more reliably prevents degradation of BT characteristics. The nitride insulating film may be formed of a silicon oxynitride film and the oxide insulating film may be formed of a silicon thermal oxidation film.
The integral formation of the oxide insulating film and the sidewalls can simplify the manufacturing steps and provide satisfactory productivity since the oxide insulating film and the sidewalls need not be formed individually. It is preferable that the interface between the gate insulating film and each sidewall is close to the interface between the channel area and each source/drain area.
It is also preferable that the interface between the nitride insulating film and each oxide insulating film is close to the interface between the channel area and each source/drain area.
In addition, preferably, the interface between each lightly doped source/drain area and each deeply doped source/drain area is close to each outer side surface of the sidewalls.
Such a MOS transistor can be manufactured by forming a nitride insulating film on a surface of silicon substrate, forming a gate electrode in a predetermined pattern on a surface of the nitride insulating film, performing wet etching of the nitride insulating film with the gate electrode used as a mask, forming an oxide insulating film thicker than the nitride insulating film under each of both end portions of the gate electrode where the nitride insulating film is removed, forming lightly doped source/drain areas in surface portions of the silicon substrate with the gate electrode used as a mask, forming sidewalls on the lightly doped source/drain areas, and forming deeply doped source/drain areas in surface portions of the silicon substrate with the sidewalls used as masks.
By this method, the oxide insulating film thicker than the nitride insulting film can be readily formed, and the MOS transistor of the LDD structure as mentioned above can be easily manufactured.
Alternatively, after the wet etching of the nitride insulating film, lightly doped source/drain areas may be formed in surface portions of the silicon substrate with the gate electrode used as a mask, by a CVD method sidewalls may be formed on the source/drain areas and an oxide insulating film is formed integrally with the sidewalls under each of both end portions of the gate electrode where the nitride insulating film is removed, and then deeply doped source/drain areas may be formed in surface portions of the silicon substrate with the sidewalls used as masks.
The step of performing wet etching preferably removes a portion of the nitride insulating film not masked by the gate electrode and removes portions of the nitride insulating film under both end portions of the gate electrode.
The above and other objects, features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.